The present disclosure relates to a high density contact arrangement. More particularly, the disclosure relates to a high density contact arrangement that facilitates the construction of high signal count integrated circuit chip assemblies.
Integrated circuit (IC) chips are often mounted to substrates in the construction of chip assemblies (e.g., flip chip assemblies). In the fabrication of such assemblies, an IC chip is provided with a plurality of contacts for delivery of both signals and power to the chip. The substrate to which the IC chip mounts is similarly provided with a plurality of signal and power contacts. In particular, the substrate is provided with a mirror image arrangement of contacts such that the contacts of the IC chip align with those of the substrate when the chip is disposed on the substrate surface.
FIG. 1 illustrates an example prior art substrate 100 used in the construction of such chip assemblies. As is shown in this figure, the substrate 100 includes a silicon die 102 that is disposed in the center of the substrate. The die 102 is provided with a plurality of contacts 104 that are separately used for signal and power transmission. FIG. 2 illustrates the silicon die 102 shown in FIG. 1 in greater detail. As indicated in this figure, the contacts 104 of the die 102 are normally arranged in aligned, linear rows 200 and columns 202. As is known in the art, each of the contacts 104 is positioned atop an opening (not visible) formed in the die""s surface through which signals and power are routed into the substrate 100. During fabrication of the substrate 100, conductive lines (e.g., silk screened conductors) 300 are extended perpendicularly outward from the die 102 within the substrate 100 as indicated in FIG. 3. As shown in this figure, these lines 300 are separated by a pitch distance, P. Due to the large number of contacts 104 provided in the rows 200 and columns 202, the conductive lines are normally closely packed around the periphery of the substrate die 102.
Manufacturers are continually increasing the number of signal contacts on substrate surfaces to increase the number of signals that can be received and transmitted by chip assemblies. As the number of signal contacts 104 grows, so too does the size of the substrate die and the IC chip that attaches to the substrate. To minimize the size of the die, and therefore the substrate and IC chip, manufacturers attempt to maximize the packing density of the contacts 104 so that more contacts can be placed within a given surface area. Such an arrangement is shown in FIG. 3. By way of example, the contacts 104 of any column 202 can be spaced so as to have a xe2x80x9cpitch,xe2x80x9d p, of approximately 225 microns (xcexcm).
Unfortunately, there are several limitations on how small this pitch dimension can be made. First, as contact spacing becomes smaller, it is more difficult to form the conductive lines that must connect to these contacts. The formation of these lines is further complicated by the columnar formation of the contacts. Specifically, it can be difficult to connect to the contacts of the columns when they are arranged in a straight line perpendicular to the edge of the die. In addition, the substrate die tends to crack when the contacts (and their associated openings) are placed too closely together. Furthermore, due to space limitations of conventional contact arrangements, the contacts are provided farther from the edge of the die as the number of contacts increases. As is known in the art, this increase in distance likewise increases impedance and resistance in the conductive lines in that these lines must be made longer to reach more distant contacts.
From the foregoing, it can be appreciated that it would be desirable to have a contact arrangement that permits high signal density and that avoids at least some of the problems identified above.
The present disclosure relates to a contact arrangement. The contact arrangement comprises a plurality of contacts formed along a line in a staggered configuration. The staggered configuration arranges the contacts so as to be diagonally spaced from each other along the line such that the contacts have an effective spacing along the line that is smaller than the actual spacing of the contacts.
In one embodiment, the contact arrangement is used to construct an integrated circuit chip assembly that comprises a substrate having a die that forms part of an outer surface of the substrate. The die is provided with a plurality of signal lines and power lines, the signal lines each including a plurality of signal contacts and the power lines each including a plurality of power contacts. The signal contacts of at least one signal line are arranged in a staggered configuration so as to be diagonally spaced from each other along the at least one signal line such that the signal contacts have an effective spacing along the at least one signal line that is smaller than the actual spacing of the signal contacts of the at least one signal line. The assembly further includes an integrated circuit chip having an outer surface comprising a plurality of contacts. The contacts of the chip are arranged in a mirror image of the contacts of the substrate such that the contacts of the chip align with the contacts of the substrate when the chip is positioned atop the substrate die.
The features and advantages of the invention will become apparent upon reading the following specification, when taken in conjunction with the accompanying drawings.